Semiconductor Packaging Method, Semiconductor Assembly and Electronic Device Comprising Semiconductor Assembly

ABSTRACT

A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device, a carrier board, and a clamping board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; and injecting a molding compound through one or more openings in one or both of the carrier board and the clamping board to form a molded package body encapsulating the at least one semiconductor device between the carrier board and the clamping board attached to the active surface of the at least one semiconductor device.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority under the Paris Convention to Chinese Patent Application No. 202011559060.9, filed Dec. 25, 2020, entitled “Semiconductor Packaging Method, Semiconductor Assembly and Electronic Device Comprising Semiconductor Assembly,” and Chinese Patent Application No. 202011573447.X, filed Dec. 25, 2020, entitled “Semiconductor Packaging Method, Semiconductor Assembly and Electronic Device Comprising Semiconductor Assembly,” each of which is incorporated by reference herein in its entirety. This application is related to co-pending U.S. patent application Ser. No. 17/535,983, filed Nov. 26, 2021, U.S. patent application Ser. No. 17/535,986, filed Nov. 26, 2021, and U.S. patent application Attorney Docket No. YB012-02US, entitled “Semiconductor Packaging Method, Semiconductor Assembly and Electronic Device Comprising Semiconductor Assembly,” filed on even date herewith, each of which is incorporated by reference herein in its entirety.

FIELD OF THE INVENTION

The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor packaging method, a semiconductor assembly and electronic device comprising the semiconductor assembly.

BACKGROUND

Semiconductor packages and systems that are compact, small, lightweight, and thin in design, while at the same time achieving high integration and versatility in function, are constantly being sought. Currently, various packaging technologies are proposed to meet the above-mentioned technical requirements, such as fan-out wafer level packaging, small chip packaging (chipset), heterogeneous integration, and 2.5-dimensional (2.5D) or three-dimensional (3D) packaging. These packaging techniques have different advantages and characteristics, but all present some technical challenges. Taking the existing fan-out package as an example, it faces many technical problems, such as warpage (warp), chip shift (die shift), surface flatness (topography), non-coplanarity between the chip and the molded package body (chip-to-mold non-planarity), package reliability (reliability), etc. Despite the continuing efforts in the industry to improve these technical problems by improving the equipment, materials, process elements, there is no economical and effective solution to some of the technical problems, especially problems such as warpage, chip drift, and surface coplanarity between different chips.

In addition, there are common techniques involved in the fabrication of various high-end semiconductor packages and systems, often involving the placement and attachment of semiconductor devices with high precision. This process step is usually performed by a high precision mounting (pick and place or die binder) equipment, which is very expensive. Still, the mounting speed is limited, resulting in low production speed, which becomes a bottleneck for the development and popularization of the technology.

The present application include some embodiments directed to solving several of the core technical problems set forth above.

SUMMARY

Certain embodiments are directed to a novel semiconductor packaging method, semiconductor device and electronic device including the semiconductor device, which at least solve the above and other problems in existing semiconductor packaging technologies.

According to some embodiments, a semiconductor packaging method comprises providing at least one semiconductor device, a carrier board, and a clamping board. In some embodiments, each of the at least one semiconductor device respectively has an active surface and an opposing passive surface, the active surface is formed with connecting terminals, and the passive surface is formed with a plurality of first alignment solder parts. In some embodiments, the carrier board is formed with a plurality of second alignment solder parts respectively corresponding to the plurality of first alignment solder parts. In some embodiments, at least one of the carrier board and the clamping board has at least one opening.

In some embodiments, the semiconductor packaging method further comprises: placing the at least one semiconductor device on the carrier board such that the plurality of first alignment solder parts are substantially aligned with respective ones of the plurality of second alignment solder parts; forming a plurality of alignment solder joints by soldering the plurality of first alignment solder parts to respective ones of the plurality of second alignment solder parts whereby the at least one semiconductor device is aligned and fixed to the carrier board; injecting a molding compound through the at least one opening to form a molded package body encapsulating the at least one semiconductor device between the carrier board and the clamping board attached to the active surface of the at least one semiconductor device; removing the clamping board to expose the connecting terminals; and sequentially forming an interconnect layer and external terminals on a surface of the molded package body where the connecting terminals are exposed, whereby the connecting terminals are electrically connected to the external terminals through the interconnect layer.

In some embodiments, the at least one opening is formed on the carrier board and is spaced apart from the second alignment solder parts.

In some embodiments, the at least one opening is formed on the clamping board and is spaced apart from the active surface of the at least one semiconductor device when the clamping board is attached to the active surface.

In some embodiments, the semiconductor packaging method further comprises attaching the clamping board to the active surface of the at least one semiconductor device.

In some embodiments, the at least one semiconductor device includes a plurality of semiconductor devices, and forming a plurality of alignment solder joints further comprises: while the plurality of semiconductor devices are aligned with the carrier board and the plurality of alignment solder joints are in a molten or partially molten state, pressing a leveling plate on the clamping board to keep the active surfaces of the plurality of semiconductor devices substantially in a same plane parallel to the carrier board until the alignment solder joints are substantially solidified, and removing the leveling plate after the plurality of alignment solder joints are substantially solidified.

In some embodiments, the at least one semiconductor device includes a plurality of semiconductor devices, and forming a plurality of alignment solder joints further comprises: while the plurality of semiconductor devices are aligned with the carrier board and the plurality of alignment solder joints are in a molten or partially molten state, applying pressure to the clamping board to keep the active surfaces of the semiconductor devices positioned in a same plane parallel to the carrier board until the plurality of alignment solder joints are substantially solidified.

In some embodiments, the at least one semiconductor device includes a plurality of semiconductor devices, the semiconductor packaging method further comprising, after forming the plurality of alignment solder joints and before injecting the molding compound: melting or partially melting the plurality of alignment solder joints, pressing a leveling plate on the clamping board to keep the active surfaces of the plurality of semiconductor devices substantially in a same plane parallel to the carrier board until the plurality of alignment solder joints are substantially solidified, and removing the leveling plate after the plurality of alignment solder joints are substantially solidified.

In some embodiments, the at least one semiconductor device includes a plurality of semiconductor devices, and forming the plurality of solder joints comprises, while the plurality of semiconductor devices are aligned with the carrier board and the plurality of alignment solder joints are in a molten or partially molten state, pressing a leveling plate on the plurality of semiconductor devices to keep the active surfaces of the plurality of semiconductor devices substantially in a same plane parallel to the carrier board until the plurality of alignment solder joints are substantially solidified, and removing the leveling plate after the plurality of alignment solder joints are substantially solidified.

In some embodiments, the at least one semiconductor device includes a plurality of semiconductor devices, the semiconductor packaging method further comprising, after forming the plurality of alignment solder joints and before injecting the molding compound: melting or partially melting the plurality of alignment solder joints, applying pressure on the clamping board to keep the active surfaces of the plurality of semiconductor devices substantially in a same plane parallel to the carrier board until the plurality of alignment solder joints are substantially solidified.

In some embodiments, one of a respective first alignment solder part and a corresponding second alignment solder part is a solder bump, and the other of the respective first alignment solder part and the corresponding second alignment solder part is a solder pad or a solder bump.

In some embodiments, at least the first or second alignment solder bumps are made of solder, and soldering is performed by melting the solder.

In some embodiments, viscous flux is pre-coated on the plurality of first and/or second alignment-solder parts, and the method further comprising: before the soldering is performed, the at least one semiconductor device together with the carrier board is turned over together as a whole so that the active surface of the at least one semiconductor device is downward faced.

In some embodiments, the semiconductor packaging method further comprises, after forming a plurality of alignment solder joints, turning the at least one semiconductor device and the carrier board together as a whole to enable the active surface to face downwards, melting or partially melting the plurality of alignment solder joints, and subsequently cooling and solidifying the plurality of alignment solder joints.

In some embodiments, the semiconductor packaging method further comprises removing the carrier board after injecting the molding compound or after sequentially forming the interconnect layer and the external terminals.

In some embodiments, the semiconductor packaging method further comprises, after the interconnect layer and the external terminal are formed, dicing the molded package body to obtain individual packages.

A semiconductor packaging method according to claim 15, further comprising: thinning the molded package body, after the carrier board is removed.

In some embodiments, the interconnect layer comprises a re-distribution layer and an under-bump metallization layer sequentially in a direction away from the connecting terminals.

Another aspect of the present application provides a semiconductor device packaged by the above semiconductor packaging method.

Yet another aspect of the present application provides an electronic device including the semiconductor device described above.

It should be understood that the above description is only an overview of the present application so that the technical solutions of the present application can be more clearly understood and implemented according to the contents of the specification. In order to make the aforementioned and other objects, features and advantages of the present application more comprehensible, embodiments of the present application are described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The present embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements.

FIG. 1 is a schematic diagram illustrating a chip drift and a chip rotation phenomenon caused by a placement misalignment or a mold flow (mold flow) push during a chip-on-chip (chip-first) fan-out type package according to the related art.

FIG. 2 shows a state diagram of Under Bump Metallization (UBM) and redistribution layer (RDL) trace position mismatch (or misalignment) formed after chip drift and rotation as shown in FIG. 1.

FIG. 3 shows a flow chart illustrating a packaging method according to some embodiments.

FIG. 4A to 4I show cross-sectional views for schematically illustrating a packaging method and a package according to some embodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The present application is intended in the following description to include at least one embodiment with reference to the accompanying drawings, in which like numerals represent the same or similar elements. Although the following description is based primarily on specific embodiments, it should be understood by those skilled in the art that the following description is intended to cover alternatives, modifications, and equivalents, which may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents, and as supported by the following description and drawings. In the following description, certain specific details are set forth, such as specific configurations, compositions, and processes, etc., to provide a thorough understanding of the present application. In other instances, well-known process and manufacturing techniques have not been described in detail to avoid unnecessarily obscuring the present application. Furthermore, the various embodiments shown in the figures are schematic representations and are not necessarily drawn to scale.

Semiconductor components (which may also be referred to as semiconductor packages) are a core component of modern electronic devices or products. Semiconductor components can be broadly classified in terms of device number and density into: discrete semiconductor devices, i.e., single chip devices, such as a single digital logic processor, diode, transistor; multi-chip components, such as a module of image sensors (CIS) and image processors (ASIC), a stack of a Central Processing Unit (CPU) and a dynamic memory (DRAM); and system level components, such as radio frequency Front End Modules (FEMs) in cell phones, display screen modules in cell phones and smart watches. Generally, the system-level package can include a wide variety of devices, including passive components (resistors, capacitors, inductors) and other devices or even components, in addition to semiconductor devices.

The semiconductor components herein may include active and passive devices including, but not limited to, active devices such as bipolar transistors, field effect transistors, integrated circuits, and passive devices such as chip resistors, capacitors, inductors, Integrated Passive Devices (IPDs), micro-electro-mechanical systems (MEMS), and the like. Various electrical connections are established between various active and passive devices to form circuits that enable the semiconductor assembly to perform high speed calculations and other useful functions.

Currently, semiconductor manufacturing typically involves two complex manufacturing processes, namely front-end wafer fabrication and back-end packaging, each of which may involve hundreds of steps. Previous wafer fabrication involves forming a plurality of chips (die) on the surface of the wafer. Each chip is generally identical and contains internally the circuits formed by the electrical connections of the active and/or passive elements. Subsequent packaging involves separating individual chips from the finished wafer and packaging them into semiconductor assemblies to provide electrical connections, structural support, heat dissipation, and environmental isolation, while facilitating subsequent assembly of the electronic product.

An important goal of semiconductor manufacturing is to produce smaller semiconductor devices, packages, and assemblies. Smaller sizes, generally higher integration, less power consumption, higher performance, and smaller area/volume, are important to the performance of the final product. In one aspect, wafer fabrication can be improved to shrink chip sizes, increase circuit density and/or improve performance. In another aspect, subsequent packaging can be improved to further reduce the sizes, increase the density, and improve the performance of the semiconductor assembly by improving the packaging design, process and packaging material.

In the back-end packaging process, a novel and efficient packaging method is the so-called fan-out packaging. Fan-out packaging is a packaging technique that wraps single or multiple qualified chips (die) from a diced wafer with a molding compound and routes interconnect traces from the chip's interconnect pads to external solder balls via a redistribution layer (RDL) to achieve higher I/O density and flexible integration. The fan-out type package may be mainly classified into a chip-first type package and a chip-last type package. Chip-first type packages can be classified into a face-down type and a face-up type.

The chip-first/face-down type packaging mainstream process comprises the following main steps: picking up chips from the cut wafer and placing the chips on a carrier board pasted with an adhesive film so that an active surface of the chips faces the adhesive film; encapsulating the chips using a molding compound; removing the carrier board (together with the adhesive film) to expose the active surface of the chip; forming an interconnect layer (including an RDL layer and Under Bump Metallization (UBM)) on an active surface of a chip; forming solder balls on the interconnect layer, wherein the interconnect pads or the interconnect bumps of the chip are electrically connected with the solder balls through the interconnect layer; and dicing to form individual semiconductor elements.

The chip-first/face-up type packaging process and the chip-first/face-down type packaging process can be approximately the same, and the main difference is as follows: picking up a chip and placing the chip on a carrier board pasted with an adhesive film, wherein the active surface of the chip is opposite to (or facing away from) the adhesive film; thinning the molded package body on one side of the active surface of the chip after encapsulation to expose the interconnect bumps on the active surface of the chip; and the carrier board may be removed after the formation of the interconnect layer and the solder balls.

In the technical problem faced by the fan-out package at present, the high-precision placement and position fixing of the chip still lack an efficient and economical method. The higher the chip placement accuracy, the higher the equipment cost, the lower the production efficiency, and the more difficulty in breaking through the 0.5 micron limit of the chip mounting equipment. In addition, after a chip is placed on the adhesive film, which is used for bonding and fixing the chip, the flowing of the molding material can push the chip in the encapsulation process, so that the chip can be displaced and rotated on the adhesive film due to the deformability of the adhesive film. The higher temperatures used in the molding or encapsulation process further exacerbate this problem. Another source of chip displacement and rotation is internal stresses within the molded structure (the structure in which the chip and carrier are encapsulated d in a molding compound). Specifically, in the existing chip-first/face-down type packaging process, the encapsulation process comprises three stages: heating and injection molding, partial curing of a encapsulation material in high-temperature, and cooling, which are usually followed by a constant temperature heating step to fully cure the molding compound. The thermal expansion coefficients of the chip, the molding compound, the adhesive film, the carrier board, and the like are different, so the mismatch of the thermal expansion coefficients of various materials and the curing shrinkage of the molding compound in the encapsulation process cause uneven internal stress of the molding compound, which further causes chip drift and/or rotation (as shown in the chip arrangement at the lower right of FIG. 1) and warpage of the molded package body. Chip drift and/or rotation in turn causes positional mismatch or misalignment of subsequently formed RDL traces and UBMs (as shown in FIG. 2), which can result in a significant yield drop. The warpage of the molded package body causes difficulties in subsequent packaging processes including Under Bump Metallization (UBM) and redistribution line (RDL), and in severe cases even make it impossible to continue the process.

The present application aims to provide a novel and breakthrough packaging method that can at least solve the above technical problems.

A packaging method according to some embodiments utilizes self-alignment capability of alignment solder joints (joints) between a semiconductor device and a carrier board in a molten or partially molten state of solder to automatically and precisely align the semiconductor device to a target position on the carrier board and fix the position the semiconductor device after the solder is solidified In some embodiments, first alignment solder parts are pre-formed on the passive surface (i.e. the opposite surface of the active surface with interconnect terminals, which can be interconnect or contact pad, or interconnect or contact bumps) of the semiconductor device, and corresponding second alignment solder parts are formed on the carrier board. For example, one of a first alignment solder part and a corresponding second alignment solder part can be a solder bump, while the other of the first alignment solder part and the corresponding second alignment solder part can be a solder pad or solder bump. In some embodiments, after placing the semiconductor device at the target position on the carrier board by aligning the first alignment solder parts and the second alignment solder parts with each other, one (or both) of each respective first alignment solder part and its corresponding second alignment solder part are melted to form a respective alignment solder joint. At this point, if the semiconductor device is not precisely aligned to the target position on the carrier board (i.e., the first alignment solder part and the corresponding second alignment solder part are not aligned), the alignment solder joint in a molten or partially molten (liquid or partially liquid) state should automatically and precisely guides the semiconductor device to the target position to achieve surface energy minimization according to the principle of minimum surface energy, and the fused alignment solder joint keeps the semiconductor device firmly fixed at the target position after solidification. The first and second alignment solder parts are optimally designed (in terms including but not limited to volume, geometry, composition, location, distribution, and number, etc.) to enable the most accurate, efficient, and reliable self-alignment capability. Fixing the semiconductor device on the carrier board by adopting the soldering technique instead of the adhesive film bonding technique leads to many advantages. For example, the warping problem is improved, the possible drifting and rotating problems of the semiconductor device in the encapsulation process are prevented by the firm soldering joints, the placing deviation of a certain degree can be allowed when the semiconductor device is picked up and placed in view of the self-aligning capacity of the alignment solder joint, the requirement on the placing precision of the semiconductor device (especially for chip and place or die bonder) can be obviously reduced, the picking and placing operation speed of the semiconductor device can be obviously improved, the process efficiency is improved, and the process cost is reduced.

In addition, according to some embodiments, a clamping board is utilized to abut against the active surface of the semiconductor device, and the molded packaging process is realized by performing injection molding through an opening in the carrier board supporting the side of the passive surface of the semiconductor device, or through an opening in the clamping board. Thus, compared with existing chip-first/face-up type packaging process, the molded packaging body does not need to be thinned (by, for example, grinding) or drilled to expose the interconnect bumps or the interconnect pads after the molding or encapsulation process is performed, the efficiency of the molding or encapsulation process can be improved, accidental damage to the active surface of the semiconductor device caused by thinning (for example, grinding) or drilling processes can be avoided, and the yield can be improved.

As used herein, the term “semiconductor device” may refer to a chip (also interchangeably referred to as die, integrated circuit) produced by a chip factory (fab), i.e., a chip that has not been packaged after wafer dicing and testing, and which may typically have only interconnect pads (pads) for external connection. The semiconductor device may also be a pre-processed (at least partially packaged) chip, such as a chip with interconnect bumps (bump) formed on the interconnect pads, or may have additional structures, such as stacked chips and packaged chips, as desired.

The term “active surface” as used herein generally refers to a surface on a front side of a semiconductor device having a circuit function, including interconnect pads (or interconnect bumps formed on the interconnect pads) thereon, and may also be interchangeably referred to as a front surface or a functional surface. A surface having no circuit function on an opposing back side of the semiconductor device may be interchangeably referred to as a passive surface or a back surface.

The term “connecting terminal” as used herein generally refers to an interconnect pad or an interconnect bump on the active surface of a semiconductor device.

The term “alignment solder part” as used herein generally refers to a structure that may be aligned and soldered to a corresponding other alignment solder part for alignment by soldering methods known in the art.

FIG. 3 shows a schematic flow diagram of a packaging method according to an embodiment of the present application. As shown in FIG. 3, the packaging method includes steps S310-S360, as described below.

S310: providing at least one semiconductor device, a carrier board, and a clamping board, wherein the semiconductor device respectively has an active surface and a passive surface opposite to each other, the active surface is formed with connecting terminals thereon, the passive surface is formed with a plurality of first alignment solder parts thereon, and the carrier board is formed with a plurality of second alignment solder parts respectively corresponding to the first alignment solder parts. In some embodiments, at least one of the carrier board and the clamping board has an opening for injecting a molding compound therethrough.

In some embodiments, the at least one semiconductor device includes a plurality of semiconductor devices. As an example, the plurality of semiconductor devices may include devices that are at least partially different from each other in function, size, or shape, or may be the same as each other. In some embodiments, the type and specific number of the semiconductor devices may be appropriately selected according to specific process conditions or actual requirements (for example, the size and shape of the carrier board and the semiconductor devices, the placement pitch or package size and shape of the semiconductor devices, manufacturing process specifications, functional design of semiconductor assemblies, etc.), and the present application is not particularly limited thereto.

In some embodiments, the carrier board or carrier is a glass carrier, a ceramic carrier, a metal carrier, an organic polymer material carrier, or a silicon wafer, or a combination of two or more of the above materials or the like.

In some embodiments, either one of a first alignment solder part and a corresponding second alignment solder part is an alignment solder bump and the other is an alignment pad corresponding to the alignment solder bump. In other embodiments, the first alignment solder part and the corresponding second alignment solder part are both alignment solder bumps, and the melting points of the first alignment solder part and the second alignment solder part can be the same or different. As an example, the alignment solder bumps may be pre-fabricated on a semiconductor device (e.g., a wafer) or a carrier using a bumping process (e.g., electroplating, ball-planting, stencil printing, evaporation/sputtering, etc.) known in the art. As an example, the alignment pad may be fabricated on the semiconductor device or the carrier board in advance using a deposition (e.g., metal layer)—photolithography-etching process. In some embodiments, any other solder part configuration or form may be used as long as the first and second alignment solder parts are capable of being soldered to each other for alignment purposes.

In some embodiments, the first alignment solder parts and the second alignment solder parts correspond respectively to each other in volume, size, geometry, composition, distribution, location, and number, so that the semiconductor devices can be precisely aligned to the respective target positions on the carrier board by soldering to the first alignment solder parts respectively to the second alignment solder parts.

In some embodiments, the specific volume, size, geometry, composition, distribution, location and number of the first alignment solder parts and/or the second alignment solder parts may be appropriately selected according to specific process conditions or actual requirements (for example, the size and shape of the carrier board and the semiconductor device, the placement pitch or package size and shape of the semiconductor device, etc.), and the present application is not particularly limited thereto. For example, the first alignment solder parts may be formed in substantially the same volume, size, geometry or composition for all semiconductor devices regardless of whether functions, sizes or shapes are identical to each other, and the second alignment solder parts on the carrier board may be formed in substantially the same volume, size, geometry or composition, so as to reduce the complexity of subsequent processes and improve the packaging efficiency. For another example, for semiconductor devices with different functions, sizes or shapes, the first alignment solder parts and the second alignment solder parts may be formed with different volumes, sizes, geometries or compositions so that different bond pad heights may be formed after subsequent bonding to achieve a particular function or to meet a particular requirement. In some embodiments, for a plurality of semiconductor devices, the first alignment solder parts and/or the second alignment solder parts are configured to enable active surfaces of the plurality of semiconductor devices to lie in a same plane parallel to a surface of the first carrier board after subsequent formation of alignment solder bonds or joints.

In some embodiments, the connecting terminals are interconnect pads or bumps. By way of example, the interconnect bumps may be pre-formed on interconnect pads on the semiconductor device using a bumping process known in the art (e.g., electroplating, ball-planting, stencil printing, evaporation/sputtering, etc.). For example, the interconnect bump may be in the form of a conductive pillar. In an alternative embodiment, the connecting terminal is the interconnect pad itself.

In some embodiments, the opening is formed in the carrier board and is spaced apart from the second alignment solder bump. As an example, the opening is provided outside an area defined by a target position of the at least one semiconductor device on the first carrier board. For example, in the case where a plurality of semiconductor devices are present, the opening is provided in a region between target positions of the plurality of semiconductor devices. In some embodiments, the opening is formed on the clamping board and is spaced apart from the active surface of the at least one semiconductor device when the clamping board is affixed to the active surface of the at least one semiconductor device. In some embodiments, one or more opening is formed either or each of the carrier board and the clamping board. In some embodiments, the size, geometry, number or distribution of the openings can be appropriately selected according to the process conditions related to the subsequent molding or encapsulation process or the actual requirements related to, e.g., a molding material used in the encapsulation process, and the present application is not particularly limited to the size, geometry, number or distribution of the openings as long as the injection molding can be effectively performed for the purpose of molded encapsulation.

In some embodiments, as shown in FIG. 4A, a plurality of semiconductor devices and a carrier board 420 are provided. At least two of the semiconductor devices 410, 410′ are different, e.g., different in size and/or function, among the plurality of semiconductor devices. Interconnect pads 412 are formed distributed on the active surface 411 of each semiconductor device 410 (and/or 410′) and a plurality of alignment solder bumps 414 are formed on the passive surface 413. A plurality of alignment pads 424 are formed on a surface of the carrier board 420 in corresponding positions as the alignment bumps 414 on each semiconductor device 410 (and/or 410′). An opening 428 for injection molding is formed through the carrier board 420 in a region between target positions corresponding to the semiconductor devices 410, 410′. Alternatively, passive devices may be similarly provided in addition to semiconductor devices. For example, semiconductor device 410′ shown in FIG. 4 may be replaced with a passive device.

S320: placing the at least one semiconductor device on the carrier board such that the plurality of first alignment solder parts are substantially aligned with the plurality of second alignment solder parts.

In some embodiments, “substantial alignment” may mean each first alignment solder part and the corresponding second alignment solder part contacting each other, respectively, without being precisely centered in a direction perpendicular to the passive surface. Here, “centered” is generally meant that the centers of the corresponding first and second alignment solder bumps are aligned in a direction perpendicular to the active or passive surface. It should be noted that “substantial alignment” of a first alignment solder part with the corresponding second alignment solder part means that there is at least contact between the first alignment solder part and the corresponding second alignment solder part to the extent that self-alignment is possible by virtue of the principle of minimum surface energy of the alignment solder parts in a molten or partially molten state during soldering, as described below, and thus “substantial alignment” includes a state of imprecise alignment but at least physical contact, but may not exclude a state of exact alignment.

In some embodiments, when the semiconductor device is placed on the carrier board in step S320, the passive surface of the semiconductor device faces the carrier board (i.e., the surface on which the first alignment solder part is formed), and the active surface of the semiconductor device faces away from the carrier board.

In some embodiments, as shown in FIG. 4B, semiconductor device 410 (and/or 410′) is placed on carrier board 420 such that alignment solder bumps 414 are in contact with corresponding alignment pads 424. At this time, alignment solder bump 414 may be slightly misaligned with alignment pad 424, i.e., the vertical centerline L1 of alignment solder bump 414 and the vertical centerline L2 of alignment pad 424 are not coincident.

S330: forming a plurality of alignment solder joints by soldering the plurality of first alignment solder parts to respective ones of the plurality of second alignment solder parts so that the at least one semiconductor device is precisely aligned and fixed to the carrier board.

It should be noted that “precise alignment” indicates a state where a deviation between an actual position and a target position of the semiconductor device on the carrier board is within a tolerance in the art or a preset tolerance. In some embodiments, precise alignment is achieved using the principle of minimum surface energy exhibited by the solder joint or bonds formed by soldering the first and second alignment solder parts in a molten or partially molten state during soldering. In particular, when the first alignment solder part and the second alignment solder part are in contact with each other but are not precisely centered in a direction perpendicular to the passive surface of the semiconductor device or the carrier board, in the soldering process, one of the first alignment solder part and the second alignment solder part, which is an alignment solder bump, is melted or partially melted and wets the other one of the first alignment solder part and the second alignment solder part, which is an alignment solder pad or another alignment solder bump, or both the first and second alignment solder parts melt or partially melt as alignment solder bumps, thereby forming an alignment solder joint in a molten or partially molten state In some embodiments, the alignment solder part in the molten or partially molten state tends to reshape itself based on a minimum surface energy principle to bring the first alignment solder part and the second alignment solder part closer to a centered state, thereby driving the semiconductor device which is lighter relative to the carrier board to be accurately aligned to the target position on the carrier board.

In some embodiments, after the first alignment solder part and the second alignment solder part are bonded to form a solder joint, the passive surface of the semiconductor device and the carrier board are spaced apart to form a certain space therebetween due to the height of the alignment solder joint itself (in a direction perpendicular to the passive surface of the semiconductor device or the carrier board) formed thereby.

In some embodiments, the alignment solder bump is made of solder, and the soldering may be performed by various means known in the art for melting solder, including but not limited to reflow soldering, laser soldering, high frequency soldering, infrared soldering, and the like. By way of example, soldering may be performed using a flux or a solder paste.

In some embodiments, alignment bonding bumps 414 and alignment solder pads 424 are bonded to form alignment solder joints 416, as shown in FIG. 4C. During the soldering process, an alignment solder bump 414 in a molten state wets the corresponding alignment pad 424 and self-aligns with the alignment pad 424 (i.e., the vertical center line L1 of the alignment solder bump 414 coincides with the vertical center line L2 of the alignment pad 424) based on its minimum surface energy principle, so that the semiconductor device 410 (and/or 410′) is brought into precise alignment on the first carrier board 420. After the soldering is completed, the passive surface 413 of the semiconductor device 410 (and/or 410′) is spaced apart from the first carrier board 420 to form a space therebetween.

In some embodiments, after S330, the packaging method 300 further comprises: turning over the semiconductor device and the carrier board together as a whole to enable the active surface of the semiconductor device to face downward (e.g., toward the earth), and the alignment solder joints are cooled after melting or partially melting the alignment solder joints again to solidify the alignment solder joints. In some embodiments, the alignment solder joints, which are re-melted or partially melted at this time, are moderately elongated by the weight of the semiconductor device, whereby the self-alignment accuracy can be further improved. It should be noted that the semiconductor device will not fall off the carrier board due to its own weight because of the surface energy of the alignment solder in the molten state or the partially molten state. As an alternative embodiment, in S310, viscous flux is pre-coated on the plurality of first and/or second alignment solder parts, and S330 includes: before the soldering is performed, turning over the semiconductor device and the carrier board together as a whole so that the active surface of the semiconductor device faces downward (toward the earth). In some embodiments, the alignment solder joints, which are melted or partially melted during soldering, are moderately elongated by the weight of the semiconductor device after being flipped, whereby the self-alignment accuracy can be further improved. It should be noted that, since the viscous flux adheres the semiconductor device to the carrier, the semiconductor device would not fall off from the carrier due to its own weight after being turned over. In some embodiments, before S340 described below, the semiconductor device and the carrier board together as a whole need to be flipped again.

In some embodiments, when the semiconductor device includes a plurality of semiconductor devices, S330 includes a leveling process to level the active surfaces of the plurality of semiconductor devices using a leveling plate when the semiconductor devices are precisely aligned with the carrier board and the alignment solder joints are still in a molten or partially molten state, so that the active surfaces of the semiconductor devices are leveled with respect to each other to be basically positioned in a same plane parallel to the carrier board. As an example, the leveling process includes: placing the leveling plate over the active surfaces of the plurality of semiconductor devices; pressing the leveling plate toward the carrier board such that the active surfaces of the plurality of semiconductor devices lie substantially in a same plane parallel to the carrier board; while maintaining the pressing, cooling to substantially solidify the alignment solder joints; and removing the leveling plate. As an alternative embodiment, when the at least one semiconductor device includes a plurality of semiconductor devices, after S330, the packaging method 300 further comprises performing a leveling process, including: melting or partially melting the alignment solder joints again, leveling the active surfaces of the plurality of semiconductor devices using a leveling plate so that the active surfaces of the plurality of semiconductor devices are basically positioned in a same plane parallel to the carrier board. As an example, the leveling process includes: melting or partially melting the alignment solder joints again; placing the leveling plate over the active surfaces of the plurality of semiconductor devices; pressing the leveling plate toward the carrier board such that the active surfaces of the plurality of semiconductor devices lie substantially in a same plane parallel to the carrier board; while maintaining the pressing, cooling the assembly to substantially solidify the alignment solder joints; and removing the leveling plate. It will be appreciated that since the leveling plate is not removed until the alignment solder joint has substantially solidified, the surface energy of the molten pad is prevented from restoring the semiconductor device to its original height prior to the leveling plate.

In some embodiments, as shown in FIG. 4D, after the alignment joints 416 are again brought into a molten or partially molten state by heating, and after the leveling plate P is placed on the active surfaces 411 of the plurality of semiconductor devices 410 (and/or 410′), the leveling plate P is pressed (i.e., toward the carrier board 420) to perform a pressing or leveling process to keep the active surfaces of the plurality of semiconductor devices 410, 410′ in the same plane parallel to the carrier board 420 while he alignment joints 416 are solidifying. The temperature is decreased while the pressing is maintained to solidify the alignment joints 416, and then the leveling plate P is removed.

Thus, the active surfaces of all semiconductor devices can be precisely flush and at the same height from the carrier board. It will be appreciated that a suitable pressure needs to be applied to the leveling plate such that the alignment solder joints in the molten or partially molten state are suitably deformed and the resulting vertical (with respect to the active surface of the semiconductor device or the first carrier board) displacement of the leveling plate is suitable to prevent damage to the semiconductor device. As an example, a solder trap is formed in advance around each second alignment solder part of the carrier board, thereby preventing uncontrolled random flow of excess molten solder during the leveling process.

In some embodiments, the leveling process using a leveling plate described above is combined with the solder process or the remelting process after the inversion described above. As an example, S330 is performed after turning over the semiconductor device and the carrier board together as a whole is performed in S330, or the leveling process is performed after S330 including turning over the semiconductor device and the carrier board together as a whole is performed, or turning over the semiconductor device and the carrier board together as a whole is performed after S330 including the leveling process is performed, or the leveling process is performed when the semiconductor device and the carrier board together as a whole is turned over, and the alignment solder joints are cooled after melting or partially melting the alignment solder joints again to solidify the alignment solder joints.

S340: performing injection molding through the opening to form a molded package body that encapsulate the at least one semiconductor device between the carrier board and the clamping board, which is attached to the active surface of the at least one semiconductor device in advance of step S340.

In some embodiments, not only the side surfaces of the semiconductor device are encapsulated, but the space between the passive surface of the semiconductor device and the carrier board is also filled with the molding compound.

In some embodiments, the injection molding is performed through openings formed on the carrier board and/or the clamping board.

In some embodiments, S330 includes attaching the clamping board on the active surface of the at least one semiconductor device, for example, before the leveling process. In other embodiments, after forming the plurality of alignment solder joints and before injecting the molding compound through the opening, the packaging method 300 further comprises attaching the clamping board to the active surface of the at least one semiconductor device. As an example, attaching the clamping board is performed before the leveling process. As another example, attaching the clamping board is performed after the leveling process. As yet another example, attaching the clamping board is performed after S330. In still other embodiments, the leveling plate is retained as a clamping board after the leveling process. Thus, materials required by the process can be reduced and the whole process flow can be simplified by reusing the leveling plate as the clamping board. As an example, S330 includes: when the semiconductor devices are precisely aligned with the carrier board and the alignment solder joints are still in a molten or partially molten state, the clamping board is used as a leveling plate to carry out the pressing treatment on the active surfaces of the semiconductor devices, so that the active surfaces of the semiconductor devices are basically positioned in the same plane parallel to the carrier board until the alignment solder joints are substantially solidified. As another example, after forming the plurality of alignment solder joints and before injecting the molding compound through the opening, the packaging method further comprising: melting or partially melting the alignment solder joints again, leveling the active surfaces of the plurality of semiconductor devices by using the clamping board as a leveling plate, so that the active surfaces of the plurality of semiconductor devices are basically positioned in the same plane parallel to the carrier board until the alignment solder joints are substantially solidified

In some embodiments, the molding encapsulation is performed using a molding compound of a resinous material (e.g., epoxy).

In some embodiments, as shown in FIG. 4E, after attaching the clamping board 430 on the active surfaces 412 of the semiconductor devices 410, 410′, as shown in FIG. 4F, injection molding is performed through the opening 428 of the carrier 420 or the clamping board 430, thereby forming a molded package body 440 encapsulating the semiconductor devices 410, 410′ between the carrier 420 and the clamping board 430.

S350: removing the clamping board 430 to expose the connecting terminals.

In some embodiments, the clamping board 430 is removed by stripping, etching, ablating, grinding, and the like, as known in the art.

In some embodiments, as shown in FIG. 4G, the clamping board 430 is removed from the molded package body 440 to expose the active surface 411 of the semiconductor device 410, 410′, i.e., the interconnect pads 412.

S360: sequentially forming a redistribution layer and external terminals on a surface of the molded package body wherein the interconnect terminals are exposed whereby the interconnect terminals are electrically coupled to the external terminals through the redistribution layer.

In some embodiments, the interconnect layer includes a redistribution layer (RDL) and an Under Bump Metallization (UBM) in this order in a direction away from the connecting terminal, thereby achieving conductive connection of the connecting terminal with the external terminal. In some embodiments, the interconnect layer further includes an insulating layer for achieving electrical insulation between the conductive paths, and the specific number and material of the insulating layer may be appropriately selected according to specific process conditions or needs, which is not particularly limited in the present application.

In some embodiments, the external terminals are solder balls or solder pads.

In some embodiments, as shown in FIG. 4H, a redistribution layer (RDL) 452, a UBM 454, and solder balls 460 are sequentially formed from bottom to top on the surface of the molding compound 440 where the interconnect pads 412 are exposed, to form conductive paths from the interconnect pads 412 to the corresponding solder balls 460. In this process, a dielectric layer 456 is also formed to achieve electrical isolation between the conductive paths, particularly when forming RDL traces 452 and/or UBM 454.

In some embodiments, the packaging method further comprises: removing the carrier board between S340 and S350 or between S350 and S360 or after S360.

In some embodiments, the carrier board is removed by lift-off, etching, ablation, grinding, and the like, as known in the art. As an example, when a lift-off process is used, the solder between the carrier board and the semiconductor device (i.e. the alignment pads) may be de-soldered to facilitate the lift-off of the carrier board from the molded package body.

In some embodiments, some or all of the alignment solder joints are also removed while or after the carrier board is removed. By way of example, some or all of the alignment solder joints may be removed by de-soldering, etching, ablating, or grinding, among other processes known in the art. In some embodiments, parts of all of the alignment solder joints are left as part of the final semiconductor assembly (i.e., the finished package) for electrical connections (e.g., power and ground), heat sinking, mechanical structures, etc.

In some embodiments, as shown in FIG. 4I, the carrier board 420 and the alignment joints 416 are removed from the molded package body 440.

In some embodiments, after removing the carrier board, the method further comprises: thinning (such as grinding, etching or ablating and the like) the molded package body, from the side where the carrier board is removed. As an example, the package body may be thinned to the passive surface of the semiconductor device, or the thinned portion comprises a portion of the semiconductor device on the passive surface side of the semiconductor device. In some embodiments, the alignment solder joints remaining after the carrier board is removed may also be removed by the thinning process, which further reduces the thickness of the final semiconductor module.

In some embodiments, passive devices are also packaged with the semiconductor device in substantially the same manner as the embodiments described above.

In some embodiments, the packaging method further comprises, after S360, dicing the package body to obtain individual packages.

It should be understood that the dicing process may be performed to fabricate individual semiconductor devices or not performed according to the packaging specifications of the semiconductor devices, including but not limited to wafer level packaging, chip level packaging, system level packaging, etc.

It is apparent that those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the application. Thus, to the extent that such modifications and variations fall within the scope of the claims and their equivalents, it is intended that the present disclosure encompass such modifications and variations as well. 

What is claimed is:
 1. A semiconductor packaging method, comprising: providing at least one semiconductor device, a carrier board, and a clamping board, wherein each of the at least one semiconductor device respectively has an active surface and an opposing passive surface, the active surface is formed with connecting terminals, the passive surface is formed with a plurality of first alignment solder parts, and the carrier board is formed with a plurality of second alignment solder parts respectively corresponding to the plurality of first alignment solder parts, and wherein at least one of the carrier board and the clamping board has at least one opening; placing the at least one semiconductor device on the carrier board such that the plurality of first alignment solder parts are substantially aligned with respective ones of the plurality of second alignment solder parts; forming a plurality of alignment solder joints by soldering the plurality of first alignment solder parts to respective ones of the plurality of second alignment solder parts to align and fix the at least one semiconductor device to the carrier board; injecting a molding compound through the at least one opening to form a molded package body encapsulating the at least one semiconductor device between the carrier board and the clamping board attached to the active surface of the at least one semiconductor device; removing the clamping board to expose the connecting terminals; and sequentially forming an interconnect layer and external terminals on a surface of the molded package body where the connecting terminals are exposed, whereby the connecting terminals are electrically connected to the external terminals through the interconnect layer.
 2. The semiconductor packaging method according to claim 1, wherein the at least one opening is formed on the carrier board and is spaced apart from the second alignment solder parts.
 3. The semiconductor packaging method according to claim 1, wherein the at least one opening is formed on the clamping board and is spaced apart from the active surface of the at least one semiconductor device when the clamping board is attached to the active surface.
 4. The semiconductor packaging method according to claim 1, further comprising attaching the clamping board to the active surface of the at least one semiconductor device.
 5. The semiconductor packaging method according to claim 4, wherein the at least one semiconductor device includes a plurality of semiconductor devices, and forming a plurality of alignment solder joints further comprises: while the plurality of semiconductor devices are aligned with the carrier board and the plurality of alignment solder joints are in a molten or partially molten state, pressing a leveling plate on the clamping board to keep the active surfaces of the plurality of semiconductor devices substantially in a same plane parallel to the carrier board until the alignment solder joints are substantially solidified, and removing the leveling plate after the plurality of alignment solder joints are substantially solidified.
 6. The semiconductor packaging method according to claim 4, wherein the at least one semiconductor device includes a plurality of semiconductor devices, and forming a plurality of alignment solder joints further comprises: while the plurality of semiconductor devices are aligned with the carrier board and the plurality of alignment solder joints are in a molten or partially molten state, applying pressure to the clamping board to keep the active surfaces of the semiconductor devices positioned in a same plane parallel to the carrier board until the plurality of alignment solder joints are substantially solidified.
 7. The semiconductor packaging method according to claim 4, wherein the at least one semiconductor device includes a plurality of semiconductor devices, the semiconductor packaging method further comprising, after forming the plurality of alignment solder joints and before injecting the molding compound: melting or partially melting the plurality of alignment solder joints, pressing a leveling plate on the clamping board to keep the active surfaces of the plurality of semiconductor devices substantially in a same plane parallel to the carrier board until the plurality of alignment solder joints are substantially solidified, and removing the leveling plate after the plurality of alignment solder joints are substantially solidified.
 8. The semiconductor packaging method according to claim 1, wherein the at least one semiconductor device includes a plurality of semiconductor devices, the semiconductor packaging method further comprising, after forming the plurality of alignment solder joints and before injecting the molding compound: melting or partially melting the plurality of alignment solder joints, pressing a leveling plate on the plurality of semiconductor devices to keep the active surfaces of the plurality of semiconductor devices substantially in a same plane parallel to the carrier board until the plurality of alignment solder joints are substantially solidified, and removing the leveling plate after the plurality of alignment solder joints are substantially solidified.
 9. The semiconductor packaging method according to claim 1, wherein the at least one semiconductor device includes a plurality of semiconductor devices, and forming the plurality of solder joints comprises, while the plurality of semiconductor devices are aligned with the carrier board and the plurality of alignment solder joints are in a molten or partially molten state, pressing a leveling plate on the plurality of semiconductor devices to keep the active surfaces of the plurality of semiconductor devices substantially in a same plane parallel to the carrier board until the plurality of alignment solder joints are substantially solidified, and removing the leveling plate after the plurality of alignment solder joints are substantially solidified.
 10. The semiconductor packaging method according to claim 1, wherein the at least one semiconductor device includes a plurality of semiconductor devices, the semiconductor packaging method further comprising, after forming the plurality of alignment solder joints and before injecting the molding compound: melting or partially melting the plurality of alignment solder joints, applying pressure on the clamping board to keep the active surfaces of the plurality of semiconductor devices substantially in a same plane parallel to the carrier board until the plurality of alignment solder joints are substantially solidified.
 11. A semiconductor packaging method according to claim 1, wherein one of a respective first alignment solder part and a corresponding second alignment solder part is a solder bump, and the other of the respective first alignment solder part and the corresponding second alignment solder part is a solder pad or a solder bump.
 12. A semiconductor packaging method according to claim 12, wherein at least the first or second alignment solder bumps are made of solder, and soldering is performed by melting the solder.
 13. A semiconductor packaging method according to claim 13, wherein viscous flux is pre-coated on the plurality of first and/or second alignment-solder parts, and the method further comprising: before the soldering is performed, the at least one semiconductor device together with the carrier board is turned over together as a whole so that the active surface of the at least one semiconductor device is downward faced.
 14. A semiconductor packaging method according to claim 1, further comprising, after forming a plurality of alignment solder joints: turning the at least one semiconductor device and the carrier board together as a whole to enable the active surface to face downwards, melting or partially melting the plurality of alignment solder joints, and subsequently cooling and solidifying the plurality of alignment solder joints.
 15. A semiconductor packaging method according to claim 1, further comprising, removing the carrier board after injecting the molding compound or after sequentially forming the interconnect layer and the external terminals.
 16. A semiconductor packaging method according to claim 15, further comprising: after the interconnect layer and the external terminal are formed, dicing the molded package body to obtain individual packages.
 17. A semiconductor packaging method according to claim 15, further comprising: thinning the molded package body, after the carrier board is removed.
 18. A semiconductor packaging method according to claim 1, wherein the interconnect layer comprises a re-distribution layer and an under-bump metallization layer sequentially in a direction away from the connecting terminals.
 19. A semiconductor component made by the semiconductor packaging method according to claim
 1. 20. An electronic device comprising the semiconductor component of claim
 19. 